Circuit designers of multi-Gigabit systems face a number of challenges as advances in technology mandate increased performance in high-speed systems. For example, chip-to-chip data transfer rates have traditionally been constrained by the bandwidth of the input/output (IO) circuitry in the transmitting and receiving components. However, innovations in IO circuitry have shifted designers' attention from circuit-based limitations to the bandwidth-limiting characteristics of the transmission channel.
At a basic level, data transmission between functional blocks within a single semiconductor device or between multiple components on a printed circuit board may be represented by the system 100 shown in FIG. 1. In FIG. 1, a transmitter 102 (e.g., a microprocessor) sends data over a data channel 104 (e.g., a copper trace on a printed circuit board) to a receiver 106 (e.g., another processor or memory). Because in many synchronous systems it will be necessary to synchronize the data at the receiver, the transmitter may also send a clock signal over its own clock channel 105. Such an arrangement is particularly useful when the receiver 106 comprises a Synchronous Dynamic Random Access Memory (SDRAM), in which case there will typically be a plurality of data channels 104 corresponding to a byte or word of data.
When data is sent from an ideal transmitter 102 to a receiver 106 across an ideal (lossless) channel 104, all of the energy in the transmitted pulse will be contained within a single time cell, which is an example of what is referred to hereinafter as a unit interval (UI). However, real transmitters and real transmission channels do not exhibit ideal characteristics, and in many high-speed circuit designs, the transfer functions of the channels should also be considered. Due to a number of factors, including, for example, the dielectric medium of the printed circuit board, discontinuities introduced by vias, lossiness of the channel 104 at higher frequencies, non-uniform group delay or non-linear phase response of the channel, etc., the initially well-defined digital pulse sent over such a channel 104 will tend to spread or disperse as it passes over the transmission path. This is shown in the simulation of FIG. 2A.
In FIG. 2A, two ideal pulses, π1 and π2, each occupy their own adjacent unit intervals (UI3 and UI4). The resulting dispersed pulses, P1 and P2, represent simulated received versions of the ideal pulses after transmission at 10 Gb/s through a 6-inch copper trace in a standard printed circuit board material (FR4). As shown, the majority of P1 is received by the receiver 106 during UI3. However, because of the effect of the channel 104, this data pulse P1 spreads over multiple UIs at the receiver 106. In other words, some portion of the energy of the pulse is observed outside of the UI in which the pulse was sent (e.g., in UI3). This residual energy outside of the UI of interest may perturb another pulse otherwise occupying either of the neighboring UIs, in a phenomenon referred to as intersymbol interference (ISI). The dispersion in each of the pulses P1 and P2 overlaps the other pulse, as shown by the hatched portions in the drawings, which represent ISI.
FIG. 2B illustrates the effects of ISI on an un-encoded (NRZ signal), and particularly shows the problem of DC creep resulting from ISI. Shown is an ideal signal 20 as would be sent from the transmitter 102. The transmission of this ideal signal 20 was simulated as passing through a channel (e.g., 104) with a specified transfer function essentially mimicking that of a lossy and bandwidth-limited trace on a typical printed circuit board. Because frequency components within the ideal signal 20 are approaching the frequency limit of the channel 104, it can be seen that the resulting signal 22 is “smeared” and does not well represent the ideal signal 20. Obviously, such a poor representation of the data reduces the sensing margins at the receiver 106.
DC creep makes sensing further difficult. As one skilled in the art understands, DC creep tends to draw ISI-affected signals higher or lower in potential over time. Whether the average signal level creeps up or down depends on the predominant logic states within the signal: if the signal contains a predominant number of ‘0s,’ the average signal level will creep downward; and if the signal contains a predominant number of ‘1s,’ the average signal level will creep upward. Creep in both directions is noticeable in FIG. 2B. Because the first half of the ideal signal 20 contains mostly ‘0s,’ the resulting signal 22 during that period tends to creep to lower DC levels. By contrast, the second half of the ideal signal 20 contains mostly ‘1s,’ and so it is seen that the resulting signal 22 creeps towards higher DC levels. As noted, this problem of creep further complicates sensing. If it is assumed that a single reference voltage (VREF) is used to sense the data at the receiver, creep will eventually cause some ‘1s’ to be erroneously sensed as ‘0s’ (see, e.g., points 24a), and some ‘0s’ to be erroneously sensed as ‘1s’ (see, e.g., point 24b).
Because ISI can give rise to sensing errors at the receiver 106, a number of solutions have been proposed to offset or compensate for the effects of ISI. For example, an equalizer may be employed at transmitter 102 or at receiver 106 to compensate for the anticipated effects of the channel 104. Such an equalizer, which may comprise a filter, attempts to condition the received input signal such that the effect of the channel 104 is removed. One skilled in the art will appreciate that the terms “filter,” “equalizer,” “equalization filter,” etc., may be used interchangeably in this regard. The transfer function of an ideal equalizer is the inverse of the transfer function of the channel 104, and a practical equalizer attempts to recreate this inverse frequency response. Thus, an equalizer attempts to compensate for the frequency and phase response of the channel to produce an overall frequency response that is as flat as possible over the bandwidth of the data being transmitted or a bandwidth of interest, i.e., to normalize the frequency response and minimize group delay variation or the non-linear phase response.
One practical ISI-mitigating technique includes the use of decision feedback equalization (DFE) circuitry at the receiver 106. In DFE, past sensing decisions are used to improve the reliability of future sensing decisions by off-setting either the input signal or the reference voltage to which the input signal is compared. FIG. 3A shows a DFE circuit 108 in receiver 106, and FIG. 3B illustrates the operation of the DFE circuit 108 with reference to an example waveform 30 of received data. One skilled in the art will appreciate that the DFE circuit 108 shown in FIG. 3A incorporates the concept of loop unrolling, in which a critical path is eliminated by using two comparators 110a, 110b to present outputs to multiplexer 112 based on the last detected bit being either a ‘0’ or a ‘1.’
Specifically, the DFE circuit 108 in FIG. 3A comprises comparators 110a and 110b (typically operational amplifiers or sense amplifiers), a multiplexer (mux) 112, and a flip-flop 114. An input data signal DIN 30 (from, e.g., the channel 104) is received by the DFE circuit 108 and is input to the comparators 110a and 110b. The input data signal DIN 30 is compared to two offset reference voltages at the comparators 110a and 110b. In the first comparator 110a, DIN 30 is compared to a reference voltage VREF+α, while in the second comparator 110b, DIN 30 is compared to a reference voltage VREF−α, where α is an offset (e.g., 0.05V) from a midpoint reference voltage VREF (e.g., 0.5V). Voltage values for VREF (and VREF+α and VREF−α) may be provided by a band gap reference, by a Digital-to-Analog converter (DAC), or by a simple resistor-based voltage divider network. The outputs of the comparators 110a and 110b serve as inputs to the mux 112, which outputs a decision to the flip-flop 114 where it is captured. The output of the flip-flop 114 serves as a control signal of the mux 112, and also as the output DOUT of the DFE circuit 108, which is sent to other circuitry in the receiver circuit 106.
Operation of the DFE circuit 108 can be explained with reference to the example waveform 30 of FIG. 3B. The waveform as transmitted comprises the string of bits ‘11010,” which because of ISI has become greatly dispersed as received at the DFE circuit's input. The clock signal used to sample the data is superimposed on the waveform 30 to better highlight sampled points 32a-e. Notice that absent the use of the DFE circuit 108, at least one of the sampled data points of the waveform, 32c, a logic ‘0’ bit, would have been erroneously sampled as a logic ‘1’ because its value exceeds an otherwise midpoint reference voltage, VREF. However, data point 32c is correctly sampled when the DFE circuit 108 operates. Note that the preceding data point, 32b, comprises a logic ‘1.’ This value is latched by the flip-flop 114, and this logic state chooses the upper input to the mux 112, i.e., the output of comparator 110a. Notice that comparator 110a has an increased reference voltage (VREF+α). This increased reference value makes it more likely that the next data point (32c) will be sampled as a logic ‘0,’ which is desired because ISI and DC creep would otherwise tend to increase subsequent data bits toward a logic ‘1.’ When comparator 110a is chosen, data point 32c is compared to VREF+α, and because data point 32c is lower than this reference, it is correctly sensed as a logic ‘0.’ Because 32c is correctly sensed as a logic ‘0,’ the feedback loop in the DFE circuit 108 will now choose comparator 110b as the comparator to be used in sensing the next data point 32d. Because comparator 110b has a decreased reference voltage (VREF−α), the next data point 32d is more likely to be sensed as a logic ‘1,’ thus countering the tendency of previous data point 32c (logic ‘0’) to draw future bits to a lower voltage level, etc.
In synchronous data transfer systems such as that depicted in FIG. 1, it is becoming preferable to transmit the data (on data channel 104) with a clock (on clock channel 105) having a lower frequency than that of the data. This is beneficial for a number of reasons: first, a lower frequency clock reduces the amount of power necessary for clock generation at the transmitter 102; second, a lower frequency clock is less attenuated by high-frequency channel loss; and third, a lower frequency clock is less likely to accumulate significant jitter.
Unfortunately, a fractional-rate clock, such as a half-rate clock having one-half the frequency (relative to the data rate), does not work with the DFE circuit 108 of FIG. 3A for the obvious reason that the frequency of the clock does not match the frequency of the data. Therefore, in instances where a fractional-rate clock (on clock channel 105) is transmitted with full-rate data (on data channel 104), the DFE circuit 108 will not operate without modification. This disclosure proposes such a useful modification to allow for DFE equalization with a fractional-rate clock.